Electrical FireBibliography |
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Below are some interesting papers relevant to the work we're doing on Electrical Fire. Some key papers are in red (primary) or brown (secondary).
| Compiler Books | |||
| [ACHM82] | Engineering a Compiler: VAX-11 Code Generation and Optimization | Anklam, Cutler, Heinen, MacLaren | 82 |
| [ASU86] | Compilers: Principles, Techniques, and Tools | Aho, Sethi, Ullman | 86 |
| [Ellis86] | Bulldog: A Compiler for VLIW Architectures | Ellis | 86 |
| [Lee89] | Realistic Compiler Generation | Lee | 89 |
| [Holub90] | Compiler Design in C | Holub | 90 |
| [FraHa95] | A Retargetable C Compiler: Design and Implementation | Fraser, Hanson | 95 |
| Integrated Systems | |||
| [EAH96] | A Java ILP Machine Based on Fast Dynamic Compilation | Ebcioglu, Altman, Hokenek (IBM) | IBM Cyberjournal 8310 |
| [EbAlt96] | DAISY: Dynamic Compilation for 100% Architectural Compatibility | Ebcioglu, Altman (IBM) | IBM Cyberjournal 8502 |
| [HooZa96] | Generating Machine Specific Optimizing Compilers | Hoover, Zadeck (IBM) | POPL 96, p. 219 |
| [AGL96] | cmcc: Competitive modular compiler in C++ | Adl-Tabatabai, Gross, Lueh (CMU) | OOPSLA 96, p. 51 |
| [DDGLC96] | Vortex: An Optimizing Compiler for Object-Oriented Languages | Dean, DeFouw, Grove, Litvinov, Chambers (U Washington) | OOPSLA 96, p. 83 |
| [Brandis95] | Optimizing Compilers for Structured Programming Languages | Brandis (Zürich) | PhD thesis 95 |
| [JoMcC] | The RTL System: A Framework for Code Optimization | Johnson, McConnell (U Illinois) | |
| [McCRoSch] | The RTL System | McConnell, Roberts, Schoening (U Illinois) | |
| [FraHa91a] | A Retargetable Compiler for ANSI C | Fraser, Hanson | SIGPLAN Notices 26:10, Oct 91, p. 29 |
| [Horwat88] | A Concurrent Smalltalk Compiler for the Message-Driven Processor | Horwat (MIT) | TR 88 - 1080 |
| [Horwat89] | Concurrent Smalltalk on the Message-Driven Processor | Horwat (MIT) | TR 89 - 1321 |
| Data Structures | |||
| [BriTo93] | An Efficient Representation for Sparse Sets | Briggs, Torczon (Rice) | LOPLAS 2:1, Mar 1993, p. 59 |
| Dataflow Analysis and Intermediate Representations | |||
| Traditional | |||
| [TjiaHe92] | Sharlit -- A tool for building optimizers | Tjiang, Hennessy (Stanford) | PLDI 92, p. 82 |
| [BGS95a] | GURRR: A Global Unified Resource Requirements Representation | Berson, Gupta, Soffa | IR 95, p. 23 |
| [Tjiang93] | Automatic Generation of Data-Flow Analyzers: A Tool for Building Optimizers | Tjiang | PhD thesis 93 |
| [DRZ92] | How to Analyze Large Programs Efficiently and Informatively | Dhamdhere, Rosen, Zadeck | PLDI 92, p. 212 |
| [MaRy90] | An Efficient Hybrid Algorithm for Incremental Data Flow Analysis | Marlowe, Ryder (Rutgers) | POPL 90, p. 184 |
| [JaiTho88] | An Efficient Approach to Data Flow Analysis in a Multiple Pass Global Optimizer | Jain, Thompson (HP) | PLDI 88, p. 154 |
| Program Dependence Graphs | |||
| [BaMa92] | Program Dependence Graphs for the Rest of Us | Ballance, Maccabe (U New Mexico) | TR 92-10 |
| [WCES94] | Value Dependence Graphs: Representation Without Taxation | Weise, Crew, Ernst, Steensgaard (Microsoft) | POPL 94, p. 297 |
| [Ruf95] | Optimizing Sparse Representations for Dataflow Analysis | Ruf (Microsoft) | IR 95, p. 50 |
| Static Single Assignment: Basics | |||
| [LeTa79] | A Fast Algorithm for Finding Dominators in a Flowgraph | Lengauer, Tarjan (Stanford) | TOPLAS 1:1, Jul 79, p. 121 |
| [CFRWZ89] | An Efficient Method of Computing Static Single Assignment Form | Cytron, Ferrante, Rosen, Wegman, Zadeck (IBM) | POPL 89, p. 25 |
| [CFRWZ91] | Efficiently Computing Static Single Assignment Form and the Control Dependence Graph | Cytron, Ferrante, Rosen, Wegman, Zadeck (IBM) | TOPLAS 13:4, Oct 91, p. 451 |
| [CyFe93] | Efficiently Computing phi-Nodes On-The-Fly | Cytron, Ferrante | Langs and Compilers for Parallel Computing 93, p. 461 |
| Static Single Assignment: DJ Graphs | |||
| [SGL95a] | Incremental Computation of Dominator Trees | Sreedhar, Gao, Lee (McGill) | IR 95, p. 1 |
| [SGL96] | A New Framework for Exhaustive and Incremental Data Flow Analysis Using DJ Graphs | Sreedhar, Gao, Lee (McGill) | PLDI 96, p. 278 |
| [SGL95b] | Efficient Data Flow Analysis Using DJ Graphs: Elimination Methods Revisited | Sreedhar, Gao, Lee (McGill) | TR 95-93 |
| [SreeGao95] | A Linear Time Algorithm for Placing phi-Nodes | Sreedhar, Gao (McGill) | POPL 95, p. 62 |
| [Sreedhar95] | Efficient Program Analysis Using DJ Graphs | Sreedhar (McGill) | PhD thesis 95 |
| Static Single Assignment: Other Variants | |||
| [Ramalingam97] | On Sparse Evaluation Representations | Ramalingam (IBM) | Fourth International Static Analysis Symposium 97 |
| [PBJMS91] | Dependence Flow Graphs: An Algebraic Approach to Program Dependencies | Pingali, Beck, Johnson, Moudgill, Stodghill (Cornell) | POPL 91, p. 67 |
| [JPP94] | The Program Structure Tree: Computing Control Regions in Linear Time | Johnson, Pearson, Pingali (Cornell) | PLDI 94, p. 171 |
| [JoPi93] | Dependence-Based Program Analysis | Johnson, Pingali (Cornell) | PLDI 93, p. 78 |
| [CCF91] | Automatic Construction of Sparse Data Flow Evaluation Graphs | Choi, Cytron, Ferrante (IBM) | POPL 91, p. 55 |
| [CliPa95] | A Simple Graph-Based Intermediate Representation | Click, Paleczny | IR 95, p. 35 |
| [TuPa95] | Efficient Building and Placing of Gating Functions | Tu, Padua (U Illinois) | PLDI 95, p. 47 |
| [Havlak93] | Construction of Thinned Gated Single-Assignment Form | Havlak | Langs and Compilers for Parallel Computing 93, p. 477 |
| [GeWoSto] | A Reference Chain Approach for Live Variables | Gerlek, Wolfe, Stoltz (OGI) | |
| [SGW94] | Extended SSA with Factored Use-Def Chains to Support Optimization and Parallelism | Stoltz, Gerlek, Wolfe (OGI) | HICSS 94, p. 43 |
| [BraMö94] | Single-Pass Generation of Static Single-Assignment Form for Structured Languages | Brandis, Mössenböck (Zürich) | TOPLAS 16:6, Nov 94, p. 1684 |
| Optimization | |||
| Constant Propagation | |||
| [WeZa91] | Constant Propagation with Conditional Branches | Wegman, Zadeck (IBM) | TOPLAS 13:2, Apr 91, p. 181 |
| [SWG94] | Constant Propagation: A Fresh Demand-Driven Look | Stoltz, Wolfe, Gerlek (OGI) | SIGAPP 94 |
| Partial Redundancy Elimination | |||
| [AWZ88] | Detecting Equality of Variables in Programs | Alpern, Wegman, Zadeck | POPL 88, p. 1 |
| [RWZ88] | Global Value Numbers and Redundant Computation | Rosen, Wegman, Zadeck | POPL 88, p. 12 |
| [KRS92] | Lazy Code Motion | Knoop, Rüthing, Steffen | PLDI 92, p. 224 |
| [KRS95] | The Power of Assignment Motion | Knoop, Rüthing, Steffen | PLDI 95, p. 233 |
| [Click95a] | Global Code Motion; Global Value Numbering | Click | PLDI 95, p. 246 |
| [CliCoo95] | Combining Analyses, Combining Optimizations | Click, Cooper (Rice) | TOPLAS 17:2, Mar 95, p. 181 |
| [Click95b] | Combining Analyses, Combining Optimizations | Click (Rice) | PhD thesis 95 |
| [Simpson96] | Value-Driven Redundancy Elimination | Simpson (Rice) | PhD Thesis 96 |
| [CCKLLT97] | A New Algorithm for Partial Redundancy Elimination Based on SSA Form | Chow, Chan, Kennedy, Liu, Lo, Tu (SGI) | PLDI 97, p. 273 |
| Range Checking | |||
| [GouKlae96] | Eliminating Range Checks using Static Single Assignment Form | Gough, Klaeren | ACSC 96 |
| [GouKlae94] | Eliminating Range Checks using Static Single Assignment Form | Gough, Klaeren | Tübingen TR 94 |
| [KoWo95] | Elimination of Redundant Array Subscript Range Checks | Kolte, Wolfe | PLDI 95, p. 270 |
| [Gupta90] | A Fresh Look at Optimizing Array Bound Checking | Gupta | PLDI 90, p. 272 |
| General | |||
| [McCJo92] | Using Static Single Assignment Form in a Code Optimizer | McConnell, Johnson (U Illinois) | LOPLAS 1:2, Jun 92, p. 152 |
| [CSV95] | Operator Strength Reduction | Cooper, Simpson, Vick (Rice) | TR95635-S 95 |
| [McConnell93] | Tree-Based Code Optimization | McConnell (U Illinois) | PhD thesis 93 |
| [HHGMLH95] | Compiler Technology for Future Microprocessors | Hwu, Hank, Gallagher, Mahlke, Lavery, Haab, Gyllenhaal, August | Proc. IEEE 83:12, Dec. 95, p. 1625 |
| Synchronization | |||
| [Bacon97] | Featherweight Monitors with Bacon Bits | Bacon (IBM) | |
| Dynamic Dispatching | |||
| [DrieHö95] | Minimizing Row Displacement Dispatch Tables | Driesen, Hölzle (UCSB) | OOPSLA 95, p. 141 |
| [DMSV89] | A Fast Method Dispatcher for Compiled Languages with Multiple Inheritance | Dixon, McKee, Schweizer, Vaughan | OOPSLA 89, p. 211 |
| [ViHo96] | Compact Dispatch Tables for Dynamically Typed Object Oriented Languages | Vitek, Horspool | CC 96, p. 309 |
| [DMM96] | Simple and Effective Analysis of Statically-Typed Object-Oriented Programs | Diwan, Moss, McKinley (UMass) | OOPSLA 96, p. 292 |
| [HöUn95] | Optimizing Dynamically-Dispatched Calls with Run-Time Type Feedback | Hölzle, Ungar | PLDI 94, p. 326 |
| Interprocedural | |||
| [Hölzle94] | Adaptive Optimization for Self: Reconciling High Performance with Exploratory Programming | Hölzle | PhD thesis 94 |
| [Dolby97] | Automatic Inline Allocation of Objects | Dolby (U Illinois) | PLDI 97, p. 7 |
| [Goodwin97] | Interprocedural Dataflow Analysis in an Executable Optimizer | Goodwin (DEC) | PLDI 97, p. 122 |
| [AGS97] | Aggressive Inlining | Ayers, Gottlieb, Schooler | PLDI 97, p. 134 |
| Code Generation | |||
| [HaChri86] | High-Quality Code Generation Via Bottom-Up Tree Pattern Matching | Hatcher, Christopher (IIT) | POPL 86, p. 119 |
| [Chase87] | An Improvement to Bottom-Up Tree Pattern Matching | Chase (Rice) | POPL 87, p. 168 |
| [PeGra88] | Optimal Code Generation for Expression Trees: An Application of BURS Theory | Pelegri-Llopart, Graham (Berkeley) | POPL 88, p. 294 |
| [BDB90] | Efficient Retargetable Code Generation using Bottom-Up Tree Pattern Matching | Balachandran, Dhamdhere, Biswas | Computer Language 15:3, 1990, p. 127 |
| [FraHa91b] | A Code Generation Interface for ANSI C | Fraser, Hanson | Sw Practice and Exp 21:9, Sep 91, p. 963 |
| [FraHe91] | Hard-coding Bottom-up Code Generation Tables to Save Time and Space | Fraser and Henry | Sw Practice and Exp 21:1, Jan 91, p. 1 |
| [Proebsting92a] | Code Generation Techniques | Proebsting (U Wisconsin - Madison) | PhD thesis 92 |
| [Proebsting92b] | Simple and Efficient BURS Table Generation | Proebsting (U Wisconsin - Madison) | PLDI 92, p. 331 |
| [FraHeProe] | BURG -- Fast Optimal Instruction Selection and Tree Parsing | Fraser, Henry, Proebsting | manual |
| [FHP92] | Engineering a Simple, Efficient Code Generator Generator | Fraser, Hanson, Proebsting | LOPLAS 1:3, Sep. 92, p. 213 |
| [ProeWha96] | One-Pass, Optimal Tree Parsing -- With or Without Trees | Proebsting, Whaley (U Arizona) | CC 96, p. 294 |
| [Gough] | Bottom up Tree Rewriting with MBURG: The MBURG Reference Manual | Gough | manual |
| [NKWA96] | Code Generation = A* + BURS | Nymeyer, Katoen, Westra, Alblas | CC 96, p. 160 |
| Register Allocation | |||
| Local | |||
| [HFG89] | On the Minimization of Loads/Stores in Local Register Allocation | Hsu, Fischer, Goodman | IEEE Trans Sw Eng 15:10, Oct 89, p. 1252 |
| [BGA98] |
Linear-Time Register Allocation for a Fixed Number of Registers
|
Bodlaender, Gustedt, Arne Telle |
9th ACM/SIAM Symposium on Discrete Algorithms |
| See also instruction scheduling | |||
| Intraprocedural | |||
| [Lueh96] | Issues in Register Allocation by Graph Coloring | Lueh (CMU) | TR 96-171 |
| [LGA96] | Global Register Allocation Based on Graph Fusion | Lueh, Gross, Adl-Tabatabai (CMU) | TR 96-106 |
| [BWD95] | Register Allocation Using Lazy Saves, Eager Restores, and Greedy Shuffling | Burger, Waddell, Dybvig (Indiana) | PLDI 95, p. 130 |
| [Pinter93] | Register Allocation with Instruction Scheduling: a New Approach | Pinter (Technion) | PLDI 93, p. 248 |
| [HGAM92] | A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs | Hendren, Gao, Altman, Mukerji (McGill) | CC 92, p. 176 |
| [BGS95b] | HARE: A Hierarchical Allocator for Registers in Multiple Issue Architectures | Berson, Gupta, Soffa (U Pittsburgh) | TR 95-06 |
| [CaKo91] | Register Allocation via Hierarchical Graph Coloring | Callahan, Koblenz (Tera) | PLDI 91, p. 192 |
| [GeoApp96] | Iterated Register Coalescing | George, Appel | POPL 96, p. 208 |
| [BCT94] | Improvements to Graph Coloring Register Allocation | Briggs, Cooper, Torczon (Rice) | TOPLAS 16:3, May 94, p. 428 |
| [Briggs92] | Register Allocation via Graph Coloring | Briggs (Rice) | PhD thesis 92 |
| [ChoHe90] | The Priority-Based Coloring Approach to Register Allocation | Chow, Hennessy | TOPLAS 12, Oct 90, p. 501 |
| [ProeFi96] | Demand-Driven Register Allocation | Proebsting, Fischer | TOPLAS 18:6, Nov 96, p. 683 |
| [NoPo94] | Register Allocation Over the Program Dependence Graph | Norris, Pollock (U Delaware) | PLDI 94, p. 266 |
| [Nickerson90] | Graph Coloring Register Allocation for Processors with Multi-Register Operands | Nickerson (Intel) | PLDI 90, p. 40 |
| [FraHa92] | Simple Register Spilling in a Retargetable Compiler | Fraser, Hanson | Sw Practice and Exp 22:1, Jan 92, p. 85 |
| [GouLe95] | Register Allocation in the Gardens Point Compilers | Gough, Ledermann (Queensland) | ACSC 95 |
| [BDEO97] | Spill Code Minimization via Interference Region Spilling | Bergner, Dahl, Engebretsen, O'Keefe (U Minnesota) | PLDI 97, p. 287 |
| [LueGro97] | Call-Cost Directed Register Allocation | Lueh, Gross (CMU) | PLDI 97, p. 296 |
| Interprocedural | |||
| [Chow88] | Minimizing Register Usage Penalty at Procedure Calls | Chow | PLDI 88, p. 85 |
| [KuFi96] | Minimum Cost Interprocedural Register Allocation | Kurlander, Fischer (U Wisconsin - Madison) | POPL 96, p. 230 |
| [Wall88] | Register Windows vs. Register Allocation | Wall (Digital) | PLDI 88, p. 67 |
| Scheduling | |||
| Execution Unit Scheduling | |||
| [RauFi93] | Instruction-Level Parallel Processing: History, Overview, and Perspective | Rau, Fisher (HP) | J. Supercomputing 7, May 93, p. 9 |
| [CLMCH95] | The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors | Chang, Lavery, Mahlke, Chen, Hwu (U Illinois) | IEEE Trans on Computers 44:3, Mar 95 |
| [Griesemer92] | Scheduling Instructions by Direct Placement | Griesemer (Zürich) | CC 92, p. 229 |
| [Lam88] | Software Pipelining: An Effective Scheduling Technique for VLIW Machines | Lam (CMU) | PLDI 88, p. 318 |
| [KPF95] | Efficient Instruction Scheduling for Delayed-Load Architectures | Kurlander, Proebsting, Fischer (UWisconsin - Madison) | TOPLAS 17:5, 95, p. 740 |
| [ProeFi91] | Linear-time, Optimal Code Scheduling for Delayed-Load Architectures | Proebsting, Fischer (UWisconsin - Madison) | PLDI 91, p. 256 |
| [GooHsu88] | Code Scheduling and Register Allocation in Large Basic Blocks | Goodman, Hsu | Supercomputing 88, p. 442 |
| [BEH91] | Integrating Register Allocation and Instruction Scheduling for RISCs | Bradlee, Eggers, Henry (UWashington) | ASPLOS 91, p. 122 |
| [BHE91] | The Marion System for Retargetable Instruction Scheduling | Bradlee, Henry, Eggers (UWashington) | PLDI 91, p. 229 |
| [BeRo91] | Global Instruction Scheduling for Superscalar Machines | Bernstein, Rodeh | PLDI 91, p. 241 |
| [RGSL96] | Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler | Ruttenberg, Gao, Stoutchinin, Lichtenstein (McGill) | PLDI 96, p. 1 |
| Cache Scheduling | |||
| [HKC97] | Efficient Procedure Mapping Using Cache Line Coloring | Hashemi, Kaeli, Calder | PLDI 97, p. 171 |
| [YJKS97] | Near-Optimal Intraprocedural Branch Alignment | Young, Johnson, Karger, Smith | PLDI 97, p. 183 |
| Cross-Platform Assembly | |||
| [RaFe95] | The New Jersey Machine-Code Toolkit | Ramsey, Fernandez | Usenix 95, p. 289 |
| Dynamic Code Generation | |||
| [Engler96] | VCODE: A Retargetable, Extensible, Very Fast Dynamic Code Generation System | Engler (MIT) | PLDI 96, p. 160 |
| [LDG95] | Clarity MCode: A Retargetable Intermediate Representation for Compilation | Lewis, Deutsch, Goldstein | IR 95, p. 119 |
| [EHK96] | 'C: A Language for High-Level, Efficient, and Machine-Independent Dynamic Code Generation | Engler, Hsieh, Kaashoek (MIT) | POPL 96, p. 131 |
| [PoEngKaa] | tcc: A Template-Based Compiler for 'C | Poletto, Engler, Kaashoek (MIT) | |
| [PEK97] | tcc: A System for Fast, Flexible, and High-Level Dynamic Code Generation | Poletto, Engler, Kaashoek (MIT) | PLDI 97, p. 109 |
| [EngProe94] | DCG: An Efficient, Retargetable Dynamic Code Generation System | Engler, Proebsting | ASPLOS 94, p. 263 |
| [Morris91] | CCG: A Prototype Coagulating Code Generator | Morris | PLDI 91, p. 45 |
| [CoNoë96] | A General Approach for Run-Time Specialization and its Application to C | Consel, Noël | POPL 96, p. 145 |
| [Wall92] | Systems for Late Code Modification | Wall (Digital) | WRL report 92-3 |
| [Franz94] | Code-Generation On-the-Fly: A Key to Portable Software | Franz (Zürich) | PhD thesis 94 |
| [KEH91] | A Case for Runtime Code Generation | Keppel, Eggers, Henry (U Washington) | TR 91-11-04 |
| [Keppel91] | A Portable Interface for On-The-Fly Instruction Space Modification | Keppel (U Washington) | ASPLOS 91, p. 86 |
| [KEH93] | Evaluating Runtime-Compiled Value-Specific Optimizations | Keppel, Eggers, Henry (U Washington) | TR 93-11-02 |
| [KeRu93] | Faster Dynamic Linking for SPARC V8 and System V.4 | Keppel, Russell (U Washington) | TR 93-12-08 |
| Debugging | |||
| [Wismüller94] | Debugging of Globally Optimized Programs Using Data Flow Analysis | Wismüller | PLDI 94, p. 278 |
| [BHS92] | A New Approach to Debugging Optimized Code | Brooks, Hansen, Simmons | PLDI 92, p. 1 |
| [HCU92] | Debugging Optimized Code with Dynamic Deoptimization | Hölzle, Chambers, Ungar | PLDI 92, p. 32 |
| [RaHa92] | A Retargetable Debugger | Ramsey, Hanson | PLDI 92, p. 22 |
| Assembly Language Manuals | |||
| [Intel96a] | Pentium Pro Family Developer's Manual, Vol 2: Programmer's Reference Manual | Intel | 96 |
| [Intel96b] | Pentium Pro Family Developer's Manual, Vol 3: Operating System Writer's Manual | Intel | 96 |
| [Intel95] | Optimizations for Intel's 32-Bit Processors | Intel | 95 AP-526 |
| [Motorola87] | MC68030 Enhanced 32-Bit Microprocessor User's Manual | Motorola | 87 MC68030UM/AD |
| [Motorola89] | MC68040 32-Bit Microprocessor User's Manual | Motorola | 89 MC68040UM/AD |
| [IBMMot93] | PowerPC 601 RISC Microprocessor User's Manual | IBM, Motorola | 93 MPC601UM/AD Rev. 1 |
| [HKHW96] | The PowerPC Compiler Writer's Guide | Hoxey, Karim, Hay, Warren | 96 MPRPPCOMP-01 |
| [Heinrich93] | MIPS R4000 User's Manual | Heinrich | 93 |
| [SPARC92] | The SPARC Architecture Manual, Version 8 | SPARC International | 92 SAV080SI9106 |
| [Digital92] | Alpha Architecture Handbook | Digital | 92 |
| [Kane96] | PA-RISC 2.0 Architecture | Kane | 96 |
| Java Manuals | |||
| [ArGo96] | The Java Programming Language | Arnold, Gosling | 96 |
| [GJS96] | The Java Language Specification | Gosling, Joy, Steele | 96 |
| [LiYe97] | The Java Virtual Machine Specification | Lindholm, Yellin | 97 |
| [GoYe96a] | The Java Application Programming Interface, Vol 1: Core Packages | Gosling, Yellin | 96 |
| [GoYe96b] | The Java Application Programming Interface, Vol 2: Window Toolkit and Applets | Gosling, Yellin | 96 |
| Java Variants | |||
| [MBL97] | Parametrized Types for Java | Myers, Bank, Liskov (MIT) | POPL 97, p. 132 |
| [MBL97] | Pizza into Java: Translating Theory into Practice | Odersky, Wadler | POPL 97, p. 146 |
| [Golliver97a] | First-Implementation Artifacts in Java | Golliver | Intel 97 |
| [Golliver97b] | The Ivory Brand of Java | Golliver | Intel 97 |
